This invention relates to semiconductor devices and fabrication processes and, more specifically, to a method of fabricating silicon-on-insulator semiconductor devices.
Complementary metal oxide semiconductor (CMOS) devices comprise a combination of P-channel and N-channel transistors. These devices operate at an intermediate speed for semiconductor devices and have an intermediate component density. CMOS devices are normally fabricated from a silicon wafer that, after processing, has an integrated circuit disposed on its surface.
A conventional method of silicon-on-insulator device fabrication includes depositing a layer of silicon on the top surface of an insulator wafer, then photomasking or delineating the surface of the wafer to define the active areas. This process allows areas of material to be selectively removed from the surface of the wafer. The next step involves diffusing in dopants, that will change the silicon layer into P-type or N-type, in unprotected areas of the silicon. After these dopants are diffused in, their concentrations are adjusted using implantation. The final step is a metallization process which involves placing a thin layer of metal over the surface of the wafer, for electrical connections, then etching away the undesired metal areas from the wafer.
In fabricating conventional silicon-on-insulator CMOS devices, it has heretofore been difficult to provide stable, low leakage, high performance devices that can be fabricated utilizing existing equipment and presently available technology. In attempting to fabricate very high-speed CMOS devices that are latch-up free and radiation hardened, the processes have not proved to be easy, straight-forward, and cost effective. The conventional processes for fabricating silicon-on-insulator CMOS devices involve delineating the active areas first and then adjusting the doping concentrations by implantation. However, the active area edge may not be perfectly vertical. It is difficult to control the impurity dopant concentrations on non-vertical active edges and at the corners. Poor control of doping profiles results in high leakage. Because of high leakages, it is very difficult to achieve a high yield of CMOS devices.
It is therefore an objective of the present invention to provide a silicon-on-insulator device that has low edge and back channel current leakages. Yet another objective of the invention is to provide a fabricating process that enables good control of doping profiles. A still further objective of the present invention is to fabricate a silicon-on-insulator device providing effective control of threshold voltages. Still another objective of the present invention is to fabricate a device that has thicker source and drain regions compared to the gate region. A further objective of the invention is to provide an easy, straight forward and cost-effective process to fabricate a controllable and reliable silicon-on-insulator CMOS device that is latch-up free and radiation hardened that can be achieved using present equipment and available technology.